M37281EKSP Datasheet, PDF (70/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Block Control Register i
b7 b6 b5 b4 b3 b2 b1 b0
Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16]
B
Name
0, 1 Display mode
selection bits
(BCi0, BCi1)
Functions
b1 b0
0 0: Display OFF
0 1: OSD mode
1 0: CC mode
1 1: CDOSD mode
After reset R W
Indeterminate R W
2 Border control bit 0 : Border OFF
(BCi2)
1 : Border ON
Indeterminate R W
3, 4 Dot size selection
bits
(BCi3, BCi4)
5, 6 Pre-divide ratio
selection bit
(BCi5, BCi6)
b6 b5 b4 b3 Pre-divide
ratio
Dot size
Indeterminate R W
00
0
01
01 ⁰
✕1
11
00
0
01
1
✕2
10
11
1 10 0
01
1
00
10 ₁
✕3
10
11
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
Indeterminate R W
1.5Tc ✕ 1/2H (See note 3)
1.5Tc ✕ 1H (See note 3)
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
7 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is indeterminate.
Indeterminate R —
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit.
2: H is HSYNC.
3: This character size is available only in Layer 2. At this time, set layer 1’s
pre-divide ratio = ✕ 2, layer 1’s horizontal dot size = 1Tc.
Fig. 8.11.4 Block Control Register i (i = 1 to 16)
Rev.1.01 2003.07.16 page 70 of 170