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M37281EKSP Datasheet, PDF (39/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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M37281MAHâXXXSP,M37281MFHâXXXSP,M37281MKHâXXXSP, M37281EKSP
8.6.5 I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
(1) Bit 0: Last Receive Bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to â0.â If ACK is not returned, this bit is
set to â1.â Except in the ACK mode, the last bit value of received data
is input. The state of this bit is changed from â1â to â0â by executing a
write instruction to the I2C data shift register (address 00F616).
(2) Bit 1: General Call Detecting Flag (AD0)
This bit is set to â1â when a general callâ½ whose address data is all
â0â is received in the slave mode. By a general call of the master
device, every slave device receives control data after the general
call. The AD0 bit is set to â0â by detecting the STOP condition or
START condition.
â½General call: The master transmits the general call address â0016â
to all slaves.
(3) Bit 2: Slave Address Comparison Flag (AAS)
This flag indicates a comparison result of address data.
s In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to â1â in one of the following conditions.
⢠The address data immediately after occurrence of a START con-
dition matches the slave address stored in the high-order 7 bits
of the I2C address register (address 00F716).
⢠A general call is received.
s In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to â1â with the following condition.
⢠When the address data is compared with the I2C address regis-
ter (8 bits consists of slave address and RBW), the first bytes
match.
s The state of this bit is changed from â1â to â0â by executing a write
instruction to the I2C data shift register (address 00F616).
(4) Bit 3: Arbitration Lostâ½ detecting flag (AL)
In the master transmission mode, when a device other than the mi-
crocomputer sets the SDA to âL,â, arbitration is judged to have been
lost, so that this bit is set to â1.â At the same time, the TRX bit is set to
â0,â so that immediately after transmission of the byte whose arbitra-
tion was lost is completed, the MST bit is set to â0.â When arbitration
is lost during slave address transmission, the TRX bit is set to â0â and
the reception mode is set. Consequently, it becomes possible to re-
ceive and recognize its own slave address transmitted by another
master device.
â½Arbitration lost: The status in which communication as a master is
disabled.
(5) Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from â1â to â0.â At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to â0â in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt re-
quest signal occurs in synchronization with a falling edge of the PIN
bit. When the PIN bit is â0,â the SCL is kept in the â0â state and clock
generation is disabled. Figure 8.6.8 shows an interrupt request sig-
nal generating timing chart.
The PIN bit is set to â1â in any one of the following conditions.
⢠Executing a write instruction to the I2C data shift register (address
00F616).
⢠When the ESO bit is â0â
⢠At reset
The conditions in which the PIN bit is set to â0â are shown below:
⢠Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
⢠Immediately after completion of 1-byte data reception
⢠In the slave reception mode, with ALS = â0â and immediately after
completion of slave address or general call address reception
⢠In the slave reception mode, with ALS = â1â and immediately after
completion of address data reception
(6) Bit 5: Bus Busy Flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to â0,â this bus system is not busy and a START condition can be
generated. When this bit is set to â1,â this bus system is busy and the
occurrence of a START condition is disabled by the START condition
duplication prevention function (Note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to â1â by detecting a START
condition and set to â0â by detecting a STOP condition. When the
ESO bit of the I2C control register (address 00F916) is â0â and at
reset, the BB flag is kept in the â0â state.
(7) Bit 6: Communication Mode Specification Bit (transfer direc-
tion specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is â0,â the reception mode is selected and the data of a trans-
mitting device is received. When the bit is â1,â the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00F916) is â0â in
the slave reception mode is selected, the TRX bit is set to â1â (trans-
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mit) if the least significant bit (R/W bit) of the address data transmit-
__
ted by the master is â1.â When the ALS bit is â0â and the R/W bit is
â0,â the TRX bit is cleared to â0â (receive).
The TRX bit is cleared to â0â in one of the following conditions.
⢠When arbitration lost is detected.
⢠When a STOP condition is detected.
⢠When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
⢠With MST = â0â and when a START condition is detected.
⢠With MST = â0â and when ACK non-return is detected.
⢠At reset
Rev.1.01 2003.07.16 page 39 of 170
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