SAA6721E Datasheet, PDF (63/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Memory port clock output; pin MCLKO
f_MCLKO
C_L
δ
frequency
load capacitance
duty factor
−
−
125
MHz
−
−
20
pF
40
50
60
%
Input signal at pin MCLKI with respect to signal at pin MCLKO; see Fig.24
f_MCLKI
δ
t_PD
frequency
duty factor
propagation delay
−
−
40
50
6.5
125
MHz
60
%
10
ns
Input signals at pins DQ63 to DQ0 with respect to the negative edge of signal at pin MCLKO
t_su
set-up time
t_h
hold time
6.0
−
−
ns
−3.0
−
−
ns
Output signals at pins DQ63 to DQ0, RAS, CAS, WE, A10 to A0, and BA with respect to the negative edge of
signal at pin MCLKO; note 3
t_h
hold time
pins DQ63 to DQ0
pins RAS, CAS, WE,
A10 to A0, and BA
−1
−
−
ns
0
−
−
ns
t_PD
propagation delay
pins DQ63 to DQ0
pins RAS, CAS, WE,
A10 to A0, and BA
−
−
1.0
ns
−
−
1.0
ns
Notes
1. C_L = 15pF, I_o = 2 mA and R_L = 2 kΩ.
2. C_L = 15pF, I_o = 4 mA and R_L = 2 kΩ.
3. C_L = 10pF, I_o = 4 mA and R_L = 2 kΩ.
1999 May 11
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