SAA6721E Datasheet, PDF (22/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
ADDRESS R/W D7
D6
D5
D4
D3
D2
D1
D0
19
R
20
R non_black_lines[7 to 0]
21
R
22
R non_black_pixels[7 to 0]
23
R
black_
pixels[8]
non_black_lines[10 to 8]
non_black_pixels[11 to 8]
General configuration
24
W
25
W
intr_clear
single_ no_
adc_mode memory_
mode
yuv_clk_
mux
memory_
init
csm_
bypass
reset_
reset_
input_path memory_
path
frc_on
blank_
screen
reset_
proc_path
power_
down
Clock distribution
26
W por_mclk pre_div_ post_div_ pre_div_ post_div_ pll_enable pll_pclk pll_mclk
enable enable half_clock half_clock
27
W pre_div_clock_p_high[3 to 0]
pre_div_clock_p_low[3 to 0]
28
W pre_div_clock_n_high[3 to 0]
pre_div_clock_n_low[3 to 0]
29
W
pre_div_clock_n_offs[3 to 0]
30
W post_div_clock_p_high[3 to 0]
post_div_clock_p_low[3 to 0]
31
W post_div_clock_n_high[3 to 0]
post_div_clock_n_low[3 to 0]
32
W
post_div_clock_n_offs[3 to 0]
Input interface
33
W rgb_interl_ in_form_ rgb_proc_ adc_
gainc_pol clamp_pol vs_pol
hs_pol
on
on
on
sample_
seq
34
W
field_
reverse
yuv_field_mode
[1 and 0]
yuv_input_mode
[1 and 0]
yuv_href_ yuv_cref_
pol
pol
35
W v_offset[7 to 0]
36
W
v_offset[10 to 8]
37
W h_offset[7 to 0]
38
W
h_offset[11 to 8]
39
W v_length[7 to 0]
40
W
v_length[10 to 8]
41
W h_length[7 to 0]
42
W
h_length[11 to 8]
43
W clamp_on[7 to 0]
44
W clamp_off[7 to 0]
45
W gainc_on_delay[7 to 0]
46
W gainc_off_delay[7 to 0]
1999 May 11
22