SAA6721E Datasheet, PDF (44/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
handbook, full pagewidth
MCLKI
CLK
PRE-DIVIDER
÷2
PLL
× 32
POST-DIVIDER
MCLKO
PCLK
Fig.11 Clock generator.
MHB251
8.2.2 CLOCK DIVIDER
The pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval
from 1.5 to 10.5. All further dividing ratios are in steps of 1.0; see Fig.12 and Table 9.
Programming of the clock dividers must be done using the registers 26 to 32. It is necessary that the clock dividers must
be disabled before programming and be enabled afterwards. This can be done with pre_div_enable and
post_div_enable.
handbook, full _Cpa_Lg_Kewidth
CLK/4
CLK/4.5
CLK/5
CLK/5.5
Fig.12 Clock waveforms.
Table 9 Clock divider programming
RATIO
1.5
2.0
2.5
3.0
3.5
P-COUNTER
(HEX)
10
00
30
10
41
1999 May 11
N-COUNTER
(HEX)
10
00
30
10
41
44
N-OFFSET
COUNTER (HEX)
1
0
2
0
3
MHB252
HALF CLK
1
0
1
1
1