SAA6721E Datasheet, PDF (62/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
11 TIMING CHARACTERISTICS
V_DDD = 3.0 to 3.6 V; V_DD(PLL) = 3.1 to 3.5 V; T_amb = 25 °C; see Fig.23; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
System clock input at pin CLK
f_CLK
clock frequency
δ
duty factor
24
−
70
MHz
40
50
60
%
RGB/YUV sample clock input at pin VCLK
f_VCLK
clock frequency
δ
duty factor
single ADC mode
double ADC mode
25
−
12.5
−
40
50
150
MHz
75
MHz
60
%
Input signals at pins VVS, VHS, VPA7 to VPA0, VPB7 to VPB0, VPC7 to VPC0, VPD7 to VPD0, VPE7 to VPE0,
and VPF7 to VPF0 with respect to signal at pin VCLK
t_su
set-up time
t_h
hold time
−4.0
−
−
ns
7.0
−
−
ns
Output signals at pins CLAMP and GAINC with respect to signal at pin VCLK; note 1
t_h
hold time
t_PD
propagation delay
8
−
−
ns
−
−
13
ns
Output clock to panel at pin PCLK
f_PCLK
δ
clock frequency
duty factor
−
−
80
MHz
40
50
60
%
Output signals at pins PVS, PHS, PDE, PAR7 to PAR0, PAG7 to PAG0, PAB7 to PAB0, PBR7 to PBR0,
PBG7 to PBG0, and PBB7 to PBB0 with respect to signal at pin PCLK; note 2
t_h
hold time
pins PVS, PHS and PDE
all other pins
−0.5
−
−
ns
0
−
−
ns
t_PD
propagation delay
pins PVS, PHS and PDE
all other pins
−
−
1
ns
−
−
3.5
ns
Overlay port clock output at pin OVCLK
f_OVCLK
δ
clock frequency
duty factor
80
MHz
40
50
60
%
Input signals at pins OVACT, OVA2 to OVA0, and OVB2 to OVB0 with respect to signal at pin OVCLK
t_su(i)
set-up time
t_h(i)
hold time
6.0
−
−
ns
−3.0
−
−
ns
Output signals at pins OVVS and OVHS with respect to signal at pin OVCLK; note 1
t_h(o)
t_PD(o)
hold time
propagation delay
−1.0
−
−
−
−
ns
1.0
ns
1999 May 11
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