SAA6721E Datasheet, PDF (33/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
NAME
INTERLACED MODE PROGRAMMING
YUV CREF polarity
YUV clock qualifier is active LOW
YUV clock qualifier is active HIGH
YUV HREF polarity
Active data qualifier is active LOW
Active data qualifier is active HIGH
YUV format
CCIR 656
4 : 1 : 1 format
4 : 2 : 2 format
4 : 4 : 4 format
YUV field sampling mode
All incoming frames are captured
Capture alternating fields only
Capture odd fields only
Capture even fields only
Field reverse flag
Keep original odd field identification
Change field identification
VERTICAL SAMPLE OFFSET
Vertical sample offset from Vsync
HORIZONTAL SAMPLE OFFSET
Horizontal sample offset from Hsync
VERTICAL SAMPLE LENGTH
Vertical sample window length
HORIZONTAL SAMPLE LENGTH
Horizontal sample window length
CLAMP PULSE START
Start of clamp pulse after active edge of Hsync
CLAMP PULSE END
End of clamp pulse after active edge of Hsync
GAIN CORRECTION PULSE START DELAY
Delay of start of GAINC pulse from first edge of Hsync
GAIN CORRECTION PULSE END DELAY
Delay of end of pulse GAINC from second edge of Hsync
Preliminary specification
SAA6721E
SUBADDRESS R/W
DATA
34
W D0
logic 0
logic 1
D1
logic 0
logic 1
D3 and D2
D3 = 0 and D2 = 0
D3 = 0 and D2 = 1
D3 = 1 and D2 = 0
D3 = 1 and D2 = 1
D5 and D4
D5 = 0 and D4 = 0
D5 = 0 and D4 = 1
D5 = 1 and D4 = 0
D5 = 1 and D4 = 1
D6
logic 0
logic 1
35 and 36
W D10 to D0
37 and 38
W D11 to D0
39 and 40
W D10 to D0
41 and 42
W D11 to D0
43
W D7 to D0
44
W D7 to D0
45
W D7 to D0
46
W D7 to D0
1999 May 11
33