SAA6721E Datasheet, PDF (50/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
8.5.1 MEMORY INTERFACE LIMITATIONS
The timing parameters of the memory access can be programmed to fulfil the timing restrictions of several SDRAM or
SGRAM devices. But there are some limitations, as shown in Table 14.
Table 14 Memory interface limitations
TIMING SYMBOL
PARAMETER
CONDITIONS
CAS latency
Column Address Strobe (CAS)
latency
t_RCD
activate to command delay; Row
Address Strobe (RAS) to CAS delay
t_RRD
t_RP
t_WR
RAS to RAS bank activity delay
RAS precharge time
write recovery time
t_RRD ≠ t_RCD; proposal is
t_RRD = t_RCD + 1
t_RC
RAS cycle time
SDRAM_burst_length
must be supported by
SDRAM
burst_seq_length
must be an even number
t_RSC
Register Set Cycle (RSC) mode time internally defined; cannot be
changed
MINIMUM VALUE
(CLOCK PERIODS)
≥2
≥2
≥3
≥3
≥1
≥3
≥2
≥2
=8
8.5.2 INITIALIZATION OF EXTERNAL MEMORY
All SGRAM and SDRAM devices must be powered-up and initialized correctly. The SAA6721E memory interface is
implemented to fulfil the INTEL PC100 SDRAM specification.
Table 15 shows the required programming steps to initialize the memory correctly.
Table 15 Memory initialization programming
STEP
1
2
3
4
5
ACTION
SAA6721E Power-on reset
set-up timing parameters
start memory initialization with setting memory_init
set-up all other parameters
release internal memory reset together with other internal resets
REGISTERS
−
51 to 55
24
50 to 74
24
8.5.3 FRAME AND FIELD MEMORY
The memory interface acts as a decoupling unit to adapt the different frame rates at the video input to the panel output.
The external memory is also used for the de-interlacing unit which reconstructs the frames from odd and even fields in
interlaced mode. The algorithm of de-interlacing can be selected by deint_mode (see Table 16).
1999 May 11
50