SAA6721E Datasheet, PDF (21/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
7.9.2 DOWNSCALING
The downscaling engine is used for reducing the incoming
RGB data stream, i.e. for displaying high resolution input
frames on panels with a smaller resolution. The scaling
ratio can be programmed independently for both horizontal
and vertical downscaling units. The algorithm uses pixel
accumulation, achieving a minimum scaling factor of ¹â„₆₄.
8 SYSTEM DESCRIPTION
8.1 Programming registers
The SAA6721E is a highly integrated device with many
features. To get the desired functionality and performance
it must be programmed correctly. In general, before
programming, the device must be switched to the internal
reset state to prevent unwanted functions while changing
the registers.
After writing to all registers the internal reset can be
released. There are some registers (mainly offset
counters) that can be changed during data processing
without an internal reset. All accesses to the on screen
display can be done during data processing.
Table 6 I²C-bus device address
MSB
0
1
1
1
0
LSB
1 SAD R/W
Bit SAD = 0 the address is 74H, while bit SAD = 1 the
address is 76H.
Table 7 shows the programming model.
Table 7 Programming register overview
ADDRESS R/W D7
D6
D5
State
0
1
2
3
R reserved
R reserved
R/W iic_test_register[7 to 0]
R
RGB mode detection
4
R
5
R v_lines[7 to 0]
6
R
7
R h_clocks[7 to 0]
8
R
RGB auto-adjustment
9
W ref_line[7 to 0]
10
W
11
W ref_pixel[7 to 0]
12
W
13
W ref_colour[7 to 0]
14
R ref_pixel_red[7 to 0]
15
R ref_pixel_green[7 to 0]
16
R ref_pixel_blue[7 to 0]
17
R black_lines[7 to 0]
18
R black_pixels[7 to 0]
D4
D3
D2
D1
D0
intr
pos_
vsync
pos_
hsync
no_
vsync
v_lines[10 to 8]
h_clocks[11 to 8]
no_
hsync
ref_line[10 to 8]
ref_pixel[11 to 8]
1999 May 11
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