SAA6721E Datasheet, PDF (30/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
NAME
General configuration
CONFIGURATION REGISTER 1
Processing reset state
Processing path not in reset state
Processing path in reset state
Memory reset state
Memory path not in reset state
Memory path in reset state
Input reset state
Input path not in reset state
Input path in reset state
External memory initialization
No external memory initialization
Start external memory initialization
External memory configuration
External memory present
No external memory present
External ADC configuration
2 ADCs connected
1 ADC connected
Interrupt acknowledge
No acknowledge
Reset interrupt output to logic 1
CONFIGURATION REGISTER 2
Output interface Power-down mode
Normal processing
All outputs of output interface at LOW level
Blank screen
Normal data processing
Blank screen generation after memory interface
Output temporal dithering
No temporal dithering of output data stream
Temporal dithering of output data
Colour space conversion matrix
Conversion YUV to RGB enabled
Straight RGB processing enabled
YUV processing clock multiplexer
Clock will be applied at pin VCLK
Clock will be applied at pin MCLKI
1999 May 11
30
SUBADDRESS R/W
DATA
24
W D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
25
W D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1