SAA6721E Datasheet, PDF (48/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
handbook, full pagewidth
odd line
even line
Vsync end
line number
MHB255
1
314
2
315
3
316
4
317
5
318
6
319
7 ^offset
320 0
8
1
321 2
9
3
322 4
10
5
323 6
11
7
324 8
12
9
325 10
Fig.15 Line sampling.
8.3.5.1 Field capturing
Another problem that must be considered is frame
dropping. It is possible that the connected video source
only provides either odd or even frames, or that the video
source drops frames. Therefore the input interface must
process the incoming video stream in several ways, as
shown in Table 12.
Table 12 Field capture modes
yuv_field_mode[1 and 0]
DESCRIPTION
0
all incoming frames are
captured
1
after an odd frame the next
even frame will be
captured, and vice versa
2
capture only odd frames
3
capture only even frames
8.3.5.2 YUV clocking
VCLK, or alternatively the clock from MCLKI, is used for
clocking the input interface in YUV mode and the data path
behind the external clock. This second port will be used if
yuv_clk_mux is set to logic 1. The external clock is the
line-locked video clock from the video decoder. This clock
is gated by CREF and applied at pin VPD7. Data is only to
be sampled if this signal is asserted. Alternatively the
line-locked video clock divided by two can be used
(if provided by the decoder). In this event CREF must be
tied to logic 1 or logic 0 depending on its programmed
polarity.
1999 May 11
48