SAA6721E Datasheet, PDF (17/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
The CCIR 656 code byte contains vertical and horizontal
blanking as well as odd and even field information, the
protection bits P3 to P0 are ignored.
Table 3 CCIR 656 code byte
MSB
LSB
7
6
5
4
3
2
1
0
1 F⁽¹⁾ V⁽²⁾ H⁽³⁾ P3 P2 P1 P0
Notes
1. F = 0: odd field (field 1); F = 1: even field (field 2).
2. V = 0: in active field lines; V = 1: in field blanking.
3. H = 0: SAV (Start of Active Video);
H = 1: EAV (End of Active Video).
The sample window of the YUV input port is controlled by
four counters; horizontal and vertical offset, and horizontal
and vertical window size. The vertical offset counter starts
counting from the inactive or second edge of its
corresponding reference signal. The horizontal offset
counter starts with the active edge of the HREF signal.
7.5 TFT output port
The TFT output port consists of two pixel ports (A and B),
each containing red, green and blue colour information
with a resolution of 8 bits per colour. The first pixel port is
mapped to PAR7 to PAR0, PAG7 to PAG0, and
PAB7 to PAB0. The second port is mapped to
PBR7 to PBR0, PBG7 to PBG0, and PBB7 to PBB0.
The vertical and horizontal synchronization signals are
mapped to pins PVS and PHS. A data validation signal
framing visible pixels is available at pin PDE.
All of the above mentioned signals are synchronized to the
output clock at pin PCLK. The active edge of this clock is
programmable.
7.5.1 SINGLE PIXEL MODE
The single pixel mode is designed to support TFT panels
with single pixel input, and for direct connection of panel
link transmitters. Only the first pixel port PAR7 to PAR0,
PAG7 to PAG0, and PAB7 to PAB0 is used. The data is
applied at double the frequency in comparison to the
double pixel output mode.
7.5.2 DOUBLE PIXEL MODE
The double pixel mode is used for direct connection of TFT
panels with double pixel input. Both output ports are used.
The first pixel is applied at port A, and the second at port B.
7.6 Memory port
The memory port connects the SAA6721E to the external
frame buffer. This frame memory can be built from either
1M × 16 SDRAM or 256k × 32 SGRAM devices.
Supported are RAM devices with clock frequencies up to
125 MHz. This clock can be provided either by the internal
PLL, or externally be applied to pin MCLKI.
The memory data bus is split into 4 ports:
port 0 (DQ0 to DQ15), port 1 (DQ16 to DQ31),
port 2 (DQ32 to DQ47) and port 3 (DQ48 to DQ63).
To adapt the external memory to the needs of the
application by means of memory size and bandwidth, it is
possible to scale the external memory by using only the
number of subsequent ports needed to build up the frame
buffer and to achieve the memory bandwidth. As a second
step for bandwidth optimization several speed grades of
memory devices can be used.
7.6.1 SDRAM MEMORY CONFIGURATION
SDRAMs are available in sizes from 16 Mbits. For this
application a wide data bus is required, so that at least
1M × 16 devices must be used. To achieve the desired
bandwidth, 2 to 4 devices must be used in parallel, which
results in a frame buffer size of 4 to 8 Mbytes. But only half
of this memory will be used by the SAA6721E.
The memory port of the SAA6721E can be divided into
4 SDRAM channels. Each channel is 16 bits wide, and
provides in High Speed Channel (HSC) mode with a
125 MHz memory clock and an effective bandwidth of
228 Mbits/s. A Medium Speed Channel (MSC) with a
100 MHz memory clock gives an effective bandwidth of
182 Mbits/s, 91% effective bandwidth assumed.
Table 4 gives the channel configuration for several input
and panel resolutions.
1999 May 11
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