SAA6721E Datasheet, PDF (38/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
NAME
OSD overlay port
GENERAL CONFIGURATION
OSD overlay port activation
Overlay information will not be inserted into data stream
Overlay information will be inserted into data stream
Sync pulse generation
No sync pulses will be generated
Sync pulses will be generated
Clock edge for sampling
Data sampling at falling edge of clock at pin OVCLK
Data sampling at rising edge of clock at pin OVCLK
Clock gating
OVCLK always enabled
OVCLK enabled only during internal active video processing
Horizontal sync polarity
Active LOW horizontal sync pulse at pin OVHS
Active HIGH horizontal sync pulse at pin OVHS
Vertical sync polarity
Active LOW vertical sync pulse at pin OVVS
Active HIGH vertical sync pulse at pin OVVS
Overlay port active pixel qualifier polarity
Active LOW qualifier signal at pin OVACT
Active HIGH qualifier signal at pin OVACT
Overlay port clock polarity
Sync pulse change with respect to falling edge at pin OVCLK
Sync pulse change with respect to rising edge at pin OVCLK
OVERLAY HORIZONTAL SYNC START
Start of horizontal sync pulse with respect to left frame border
OVERLAY HORIZONTAL SYNC LENGTH
Length of horizontal sync pulse
OVERLAY HORIZONTAL SYNC LATENCY
Delay between start of horizontal sync and valid overlay data
OVERLAY WINDOW HORIZONTAL LENGTH
Horizontal length of overlay region
OVERLAY WINDOW VERTICAL OFFSET
Vertical offset of overlay region
OVERLAY WINDOW VERTICAL LENGTH
Vertical length of overlay region
SUBADDRESS R/W
DATA
99
W D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
100 and 101 W D10 to D0
102 and 103 W D10 to D0
104
W D7 to D0
105 and 106 W D10 to D0
107 and 108 W D10 to D0
109 and 110 W D10 to D0
1999 May 11
38