SAA6721E Datasheet, PDF (49/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
8.4 Video mode and synchronization signal
detection
The SAA6721E can be used to build up multi-sync
systems using an external microcontroller. Therefore
information about the input resolution and timing are
provided (see Tables 7 and 8). The flags pos_vsync and
pos_hsync show the polarity of the synchronization signals
at VVS and VHS. If they are set to logic 1 they are active
HIGH, and their active edge is the falling edge. If these
flags are set to logic 0, they are active LOW.
For detecting Video Electronic Standard Association
(VESA) Power-down modes or a not connected input, the
presence of the synchronization signals will be detected:
it can be read via no_vsync, and no_hsync. These flags
are active HIGH. The timing of the applied RGB video input
can be taken from v_lines reporting the number of lines of
a full frame. The horizontal timing can be calculated from
h_clocks. This register shows the length of a line in
numbers of reference clock periods. The reference clock is
equal to the panel clock PCLK in double pixel output mode
(48 bits in parallel), or it is half the panel clock PCLK in
single pixel output mode (24 bits in parallel).
If one of the above mentioned flags or counters changes
its value, it can be assumed that a new graphics mode has
been applied. In this case an interrupt at pin INT will be
generated. This port is active LOW. The reset can be
cleared by writing a logic 1 to intr_clear at address 24.
For adjusting the RGB input interface to a new graphics
mode, the registers of the section RGB auto adjustment
are to be used. With this auto adjustment support it is
possible to measure the number of blanking pixels and
lines between the end of the synchronization pulses and
the active video. The horizontal and vertical back porch
blanking can be read out at black_pixels and black_lines.
The number of active pixels or lines will be reported from
non_black_pixels and non_black_lines. The first value
should be used for tuning the sample clocks PLL so that
this value corresponds to the number of pixels to be
sampled horizontally in this specific graphics mode.
To distinguish between blanking and active video
ref_colour is used. If the sample values of all three colour
components are below this value the pixel is treated as a
blanking pixel, otherwise it is treated as active video.
Additionally a reference pixel can be defined with ref_line
and ref_pixel. The R, G, and B components of this pixel are
sampled and available at ref_pixel_red, ref_pixel_green,
and ref_pixel_blue. They can be used for fine tuning the
external PLL in frequency and phase and for colour gain
adjustment.
8.5 Memory interface and de-interlacer unit
The SAA6721E features a 64 bits wide synchronous
DRAM interface. Both SDRAM and SGRAM devices can
be used. There is no difference in programming when
using SDRAM or SGRAM devices. The only thing that
must be considered is the amount of frame buffer memory,
which must be enough for the specific application.
Depending on the kind of input data stream the memory
interface must be switched to YUV 4 : 2 : 2 or YUV 4 : 1 : 1
mode by setting yuv422_mode to logic 1 to enable 16 bits
per pixel processing. If this flag is set to logic 0, 24 bits per
pixel are used which is needed for RGB and YUV 4 : 4 : 4
processing. If not the whole bandwidth of the 64 bits wide
data bus is needed, the data bus can be downsized to
48 or 32 bits. This is done with the parameter data_width,
see Table 13.
Table 13 Data bus width
data_width[1 and 0]
0
1
2
PROGRAMMED BUS WIDTH
(BITS)
32
48
64
Since the different timing parameters of various RAM
device types are different, all important timing values are
programmable and must be set-up according to the used
RAM types.
To reach a high effective bandwidth all access to the
external memory is organized in bursts. The larger the
number of subsequent read or write accesses the higher
the effective bandwidth. An effective bandwidth of 91%
can be reached by doing 64 words burst accesses.
The RAM devices support a maximum internal burst
length of 8 words only, so 8 of these bursts must be run
subsequently. This can be programmed by setting up the
RAM with SDRAM_burst_length_code taken from the
specification data of the SDRAM or SGRAM. The memory
interface must be programmed to 64 words bursts by
programming the RAM burst length SDRAM_burst_length
to 8, and the number of these bursts in burst_seq_length
to 8. The internal structure of the SAA6721E is optimized
for 64 words bursts.
1999 May 11
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