SAA6721E Datasheet, PDF (42/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
NAME
GENERAL CONFIGURATION 2
Line length controlling in active video region
Line length controlling disabled
Line length controlling enabled
Line length controlling in border region
Line length controlling disabled
Line length controlling enabled
Line length controlling in top blanking region
Line length controlling disabled
Line length controlling enabled
Output interface mode
Free running output interface timing (external SDRAM required)
Synchronous output interface timing (without external SDRAM)
Blanking mode
Normal operating mode
All data outputs are at LOW level (black colour)
Output interface enabling
Output interface disabled, no data processing
Output interface enabled, normal data processing
Data qualifier generation mode
Disable pulse generation at pin PDE during vertical syncs
Enable pulse generation at pin PDE during vertical syncs
Line synchronization
Normal mode
Do not use
HORIZONTAL LINE LENGTH IN BLANKING REGION
Horizontal line length in blanking region
HORIZONTAL LINE LENGTH IN BORDER REGION
Horizontal line length in border region
HORIZONTAL LINE LENGTH IN ACTIVE VIDEO REGION
Horizontal line length in active video region
VERTICAL FRAME END
Vertical frame length
VERTICAL BORDER REGION START
Vertical start of border region
VERTICAL ACTIVE VIDEO REGION START
Vertical start of active video region
HORIZONTAL DELAY OF START OF VERTICAL SYNC
Horizontal start delay of vertical sync pulse at pin PVS
SUBADDRESS R/W
DATA
203
W D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
204 and 205 W D10 to D0
206 and 207 W D10 to D0
208 and 209 W D10 to D0
210 and 211 W D10 to D0
212 and 213 W D10 to D0
214 and 215 W D10 to D0
216 and 217 W D10 to D0
1999 May 11
42