SAA6721E Datasheet, PDF (15/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
handbook, full page_Vwi_Hdt_Sh
RGB data
blanking
GAINC
CLAMP
Fig.4 Clamp and gain correction pulses.
MHB244
7.4 YUV input port
The YUV input port supports interlaced video streams and
provides an easy connection to most common decoder
ICs. It consists of the luminance port VPA7 to VPA0, the
chrominance port VPB7 to VPB0, and eventually
VPC7 to VPC0, which are CCIR 601 level compatible
(Y: 16 to 235, and UV: 16 to 240).
Supported at this port are the formats YUV 4 : 1 : 1,
YUV 4 : 2 : 2 and YUV 4 : 2 : 2 with CCIR 656 codes
(see Table 2).
YUV 4 : 4 : 4 data can be applied at VPA7 to VPA0 (Y),
VPB7 to VPB0 (U), and VPC7 to VPC0 (V). Input data is
sampled with respect to the clock at pin VCLK if pin VPD7
(CREF) is asserted.
The start of active video data in a line is marked by the
rising edge at pin VPD6 (HREF) and the end of valid video
data is marked by the falling edge at pin VPD6. Figure 5
illustrates this at a YUV 4 : 2 : 2 example.
handbook, full pagewidth
VCLK
CREF
HREF
Y7 to Y0 XX
Y0
Y1
Y2
Y3
...
Y5
Y6 Y719
XX
UV7 to UV0 XX
U0
V0
U2
V2
... V716 U718 V718
XX
MHB245
Fig.5 CREF and HREF timing.
1999 May 11
15