SAA6721E Datasheet, PDF (51/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
Table 16 De-interlacing modes
deint_mode[1 and 0]
0
1
2
3
ALGORITHM
no de-interlacing and no filtering
de-interlacing without filtering
de-interlacing with spatial filtering
de-interlacing with temporal filtering
MEMORY NEEDS
1 frame buffer
2 field buffers
2 field buffers
4 field buffers
De-interlacing mode 0 must be selected for non-interlaced input of RGB or YUV. Only one memory area is needed,
whose start address must be programmed into field1_row and field1_column. Normally this should be logic 0 for both
values. All other modes need more than one memory area. So the other field start addresses must be programmed
(see Fig.16).
handbook, full pagewidth
field1_row/column
field1_row/column
field2_row/column
ODD FIELD
EVEN FIELD
field1_row/column
field2_row/column
field3_row/column
deint_mode 0
deint_mode 1/2
field4_row/column
ODD FIELD
EVEN FIELD
ODD FIELD
EVEN FIELD
MHB256
deint_mode 3
Fig.16 Memory usage for de-interlacing.
The memory interface addresses alternately the two banks of the SDRAM or SGRAM devices. So the memory needs for
the field stores must be calculated from the following formula:
field_memory_size[18 to 0] = number_of_pixels × _2-----×-----d----a-b--t--ay---t_-e--b--s--u-_--s-p--_-e--w--r--_-i-d-p--t--ih-x---e-(--bl---y---t--e---s----) , where
• number_of_pixels depends on the input resolution and whether it is an odd or even field
• bytes_per_pixel is 2 for YUV 4 : 2 : 2 and YUV 4 : 1 : 1; 3 for YUV 4 : 4 : 4 and RGB.
All memory addresses must be transformed into row and column addresses used by DRAMs. The column address is
formed by the 8 LSBs (field_memory_size[7 to 0]), and the row address by all the other address bits
(field_memory_size[18 to 8]). The column address must be aligned to the number of internal DRAM bursts, normally in
steps of 8 (0, 8, 16, etc.).
1999 May 11
51