SAA6721E Datasheet, PDF (18/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
Table 4 SDRAM channel configurations
INPUT
RESOLUTION
SVGA (800 × 600)
60 Hz
75 Hz
Panel
XGA⁽¹⁾
SXGA⁽²⁾
2 Mbits frame buffer needed
288 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
319 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
307 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
337 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
Notes
1. 36 MHz clock frequency.
2. 50 MHz clock frequency.
XGA (1024 × 768)
60 Hz
75 Hz
3 Mbits frame buffer needed
411 Mbits/s
bandwidth;
2 × HSC or
3 × MSC
452 Mbits/s
bandwidth;
2 × HSC or
3 × MSC
435 Mbits/s
bandwidth;
2 × HSC or
3 × MSC
476 Mbits/s
bandwidth;
3 × HSC or
3 × MSC
SXGA (1280 × 1024)
60 Hz
75 Hz
4 Mbits frame buffer needed
475 Mbits/s
bandwidth;
3 × HSC or
3 × MSC
540 Mbits/s
bandwidth;
3 × HSC or
3 × MSC
624 Mbits/s
bandwidth;
3 × HSC or
4 × MSC
705 Mbits/s
bandwidth;
4 × HSC or
4 × MSC
7.6.2 SGRAM MEMORY CONFIGURATION
SGRAM devices organized to 256k × 32 bits are available,
and feature the wide data bus for high speed applications.
With these devices a frame buffer can be built, without
wasting memory because of bandwidth. In case of
SGRAM usage, the memory data bus of the SAA6721E
can be split into 2 channels of 32 bits each.
Each channel gives, in HSC mode with 125 MHz clock
frequency, an effective bandwidth of 456 Mbits/s; and in
MSC mode, with 100 MHz clock speed, an effective
bandwidth of 364 Mbits/s.
Table 5 gives the channel configuration for several input
and panel resolutions.
Table 5 SGRAM channel configurations
INPUT
RESOLUTION
SVGA (800 × 600)
60 Hz
75 Hz
Panel
XGA⁽¹⁾
SXGA⁽²⁾
2 Mbits frame buffer needed
288 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
319 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
307 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
337 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
Notes
1. 36 MHz clock frequency.
2. 50 MHz clock frequency.
XGA (1024 × 768)
60 Hz
75 Hz
3 Mbits frame buffer needed
411 Mbits/s
bandwidth;
1 × HSC or
2 × MSC
452 Mbits/s
bandwidth;
1 × HSC or
2 × MSC
435 Mbits/s
bandwidth;
1 × HSC or
2 × MSC
476 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
SXGA (1280 × 1024)
60 Hz
75 Hz
4 Mbits frame buffer needed
475 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
540 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
624 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
705 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
1999 May 11
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