SAA6721E Datasheet, PDF (35/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
NAME
SDRAM TIMING PARAMETER 1; SEE TABLE 14
Active to read or write delay (t_RCD) in clocks
CAS latency (CL) in clocks
SDRAM TIMING PARAMETER 2; SEE TABLE 14
Precharge command period (t_RP) in clocks
Active bank A to active band B command (t_RRD) in clocks
SDRAM TIMING PARAMETER 3; SEE TABLE 14
Auto refresh, active command period (t_RC) in clocks
Write recovery time (t_WR) in clocks
FIELD 1 START ADDRESS (ROW)
Start address of field 1 in external SDRAM memory (row)
FIELD 1 START ADDRESS (COLUMN)
Start address of field 1 in external SDRAM memory (column)
FIELD 2 START ADDRESS (ROW)
Start address of field 2 in external SDRAM memory (row)
FIELD 2 START ADDRESS (COLUMN)
Start address of field 2 in external SDRAM memory (column)
FIELD 3 START ADDRESS (ROW)
Start address of field 3 in external SDRAM memory (row)
FIELD 3 START ADDRESS (COLUMN)
Start address of field 3 in external SDRAM memory (column)
FIELD 4 START ADDRESS (ROW)
Start address of field 4 in external SDRAM memory (row)
FIELD 4 START ADDRESS (COLUMN)
Start address of field 4 in external SDRAM memory (column)
OUTPUT FRAME LENGTH
Vertical length of output frame after de-interlacing unit
OUTPUT LINE LENGTH
Horizontal length of output frame after de-interlacing unit
BLANK COLOUR RED COMPONENT DEFINITION
Red colour component for blank screen generation
BLANK COLOUR GREEN COMPONENT DEFINITION
Green colour component for blank screen generation
BLANK COLOUR BLUE COMPONENT DEFINITION
Blue colour component for blank screen generation
SUBADDRESS R/W
DATA
53
W D3 to D0
D6 to D4
54
W D3 to D0
D7 to D4
55
W D3 to D0
D7 to D4
56 and 57
W D10 to D0
58
W D7 to D0
59 and 60
W D10 to D0
61
W D7 to D0
62 and 63
W D10 to D0
64
W D7 to D0
65 and 66
W D10 to D0
67
W D7 to D0
68 and 69
W D10 to D0
70 and 71
W D11 to D0
72
W D7 to D0
73
W D7 to D0
74
W D7 to D0
1999 May 11
35