SAA6721E Datasheet, PDF (43/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
NAME
HORIZONTAL DELAY OF END OF VERTICAL SYNC
Horizontal end delay of vertical sync pulse at pin PVS
HORIZONTAL SYNC PULSE START
Start of horizontal sync pulse at pin PHS
HORIZONTAL SYNC PULSE END
End of horizontal sync pulse at pin PHS
DATA QUALIFIER START
Start of border region and horizontal data qualifier at pin PDE
DATA QUALIFIER END
End of border region and horizontal data qualifier at pin PDE
HORIZONTAL ACTIVE REGION START
Start of horizontal active video region
VERTICAL SYNC PULSE END
Vertical sync pulse end at pin PVS
MAXIMUM HORIZONTAL LINE LENGTH
Maximum reachable line length for length controlling
SUBADDRESS R/W
DATA
218 and 219 W D10 to D0
220 and 221 W D10 to D0
222 and 223 W D10 to D0
224 and 225 W D10 to D0
226 and 227 W D10 to D0
228 and 229 W D10 to D0
230 and 231 W D10 to D0
232 and 233 W D10 to D0
8.2 Clock management
8.2.1 CLOCK GENERATION AND MULTIPLEXING
For normal operation the SAA6721E uses two clock
inputs; pin VCLK and pin CLK. VCLK is used as the
sample clock provided by the external ADCs or decoder.
The frequency and the sample edges of this clock depend
on the number of ADCs connected, or on the video dot
clock:
• 1 ADC mode: maximum VCLK frequency is 150 MHz
• 2 ADC mode: maximum VCLK frequency is 75 MHz.
The clock from pin CLK is used as an internal reference,
and it is the source clock for the internal PLL. The memory
clock MCLKO and panel clock PCLK are derived from the
PLL (see Fig.11):
MCLKO = ^{C----N-L---K---} × 16
PCLK = ^{C----N-L---K---} × ^3-M---2--
Where N = pre-divider ratio, M = post-divider ratio and
5 MHz ≤ ^{C----N-L---K---} ≤ 8 MHz
It is possible to drive the memory clock output directly
without the internal PLL via pin MCLKI. To achieve this the
programming flag pll_mclk must be set to logic 0.
The same is possible for the panel output clock. Therefore
the system clock CLK is used directly. The system clock is
controlled by pll_pclk which must be set to logic 0.
1999 May 11
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