SAA6721E Datasheet, PDF (32/72 Pages) NXP Semiconductors – SXGA RGB to TFT graphics engine

Philips Semiconductors
SXGA RGB to TFT graphics engine
Preliminary specification
SAA6721E
NAME
Input interface
GENERAL PROGRAMMING
Hsync polarity
Hsync is active LOW, line starts at rising edge of pin VHS
Hsync is active HIGH, line starts at falling edge of pin VHS
Vsync polarity
Vsync is active LOW, line starts at rising edge of pin VVS
Vsync is active HIGH, line starts at falling edge of pin VVS
Clamp pulse polarity
Pulse is active LOW
Pulse is active HIGH
Gain correction pulse polarity
Pulse is active LOW
Pulse is active HIGH
ADC sample sequence
ADC 0 is sampled first after Hsync (video input port A, B, C)
ADC 1 is sampled first after Hsync (video input port D, E, F)
RGB/YUV processing mode
YUV processing enabled
RGB processing enabled
Input interface activation
No data sampling
Data sampling enabled
Interlaced RGB mode
Non-interlaced RGB processing
Interlaced RGB processing
SUBADDRESS R/W
DATA
33
W D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
1999 May 11
32