SE97 Datasheet, PDF (51/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 33. Abbreviations …continued
Acronym
Description
RDIMM
Registered Dual In-line Memory Module
SMBus
System Management Bus
SO-DIMM
Small Outline Dual In-line Memory Module
SPD
Serial Presence Detect
15. Revision history
Table 34. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SE97_5
Modifications:
20090806
Product data sheet
-
SE97_4
• Section 1 “General description”, 7^th paragraph: deleted 5^th sentence
• Section 2.1 “General features”:
– 1^st bullet item: changed from “SO-DIMM” to “TSE 2002B3 DIMM ± 0.5 °C (typ.) between 75 °C
and 95 °C”
– 3^rd bullet item: changed from “3.0 µA (max.)” to “5.0 µA (max.)”
– 8^th bullet item: appended “(JEDEC PSON8 VCED-3)”
• Table 1 “Ordering information”, Table note [2] re-written
• Section 7.3.2.1 “Alarm window”:
– 1^st Advisory notification, Competitor device: appended “(CEVNT)” to end of phrase
– 1^st Advisory notification, Work-around: appended “(CEVNT)” to end of phrase
– 2^nd Advisory notification, Competitor devices: changed from “... when new UPPER or LOWER
and Event bit 3 (EOCTL) are set ... “ to “when new UPPER or LOWER Alarm Windows and the
EVENT output are set ...”
– 2^nd Advisory notification, Work-around: appended “(EOCTL = 1)” to end of phrase
• Section 7.3.2.2 “Critical trip”
– 1^st paragraph, last sentence: changed from “... through the Clear EVENT bit ...”
to “... through the Clear EVENT bit (CEVNT) ...
– Advisory notification, Competitor devices: re-written
– Advisory notification, Work-around: changed from “Wait at least 125 ms before enabling EVENT
output, Intel will change Nehalem BIOS so that T_th(crit) is set for more than 125 ms before Event
bit 3 (EOCTL) is enabled and Event value is checked.” to “Wait at least 125 ms before enabling
EVENT output (EOCTL = 1), Intel will change Nehalem BIOS so that T_th(crit) is set for more than
125 ms before EVENT output is enabled and Event value is checked.
• Section 7.7 “SMBus time-out”:
– 1^st paragraph, 2^nd sentence changed from “... holds SCL LOW more than 35 ms” to “... holds
SCL LOW between 25 ns and 35 ns”
– added 2^nd “Remark”
• Section 7.8 “SMBus Alert Response Address (ARA)”: added 2^nd “Remark”
• Table 12 “Configuration register (address 01h) bit description”, bit 8, SHMD: added “Remark” and
3 bullet items
• Table 29 “DC characteristics”:
– I_DD(AV): removed condition “V_DD = 3.0 V to 3.6 V”
– I_DD(AV): removed sub-row with condition “V_DD = 1.7 V”
– I_sd(VDD): changed Max value from “3 µA” to “5.0 µA”
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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