SE97 Datasheet, PDF (20/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.10.2.3 Read Permanent Write Protection (RPWP), Read Reversible Write Protection
(RRWP), and Read Clear Reversible Write Protection (RCRWP)
Read PWP, RWP, and CRWP allow the SE97 to be read in write protection mode. The
instruction format is the same as that of the write protection except that the 8^th bit, R/W, is
set to 1. Figure 17 shows the instruction format, while Table 7 shows the responses when
the instructions are issued.
Table 7. Acknowledge when reading the write protection
Instructions with R/W bit = 1.
Status
Instruction
ACK Address
Permanently
protected
RPWP, RRWP or
RCRWP
NACK not significant
Protected with
RWP
RRWP
RCRWP
NACK not significant
ACK not significant
RPWP
ACK not significant
Not protected
RPWP, RRWP or
RCRWP
ACK not significant
ACK
NACK
NACK
NACK
NACK
NACK
Data byte
not significant
not significant
not significant
not significant
not significant
ACK
NACK
NACK
NACK
NACK
NACK
7.10.3 Read operations
7.10.3.1 Current address read
In Standby mode, the SE97 internal address counter points to the data byte immediately
following the last byte accessed by a previous operation. If the ‘previous’ byte was the last
byte in memory, then the address counter will point to the first memory byte, and so on. If
the SE97 decodes a slave address with a ‘1’ in the R/W bit position (Figure 18), it will
issue an Acknowledge in the ninth clock cycle and will then transmit the data byte being
pointed at by the address counter. The master can then stop further transmission by
issuing a No Acknowledge on the ninth bit then followed by a STOP condition.
slave address (memory)
SDA S 1 0 1 0 A2 A1 A0 1 A
data from memory
AP
START condition
R/W acknowledge
from slave
Fig 18. Current address read timing
no acknowledge
from master
STOP condition
002aab251
7.10.3.2 Selective read
The read operation can also be started at an address different from the one stored in the
address counter. The address counter can be ‘initialized’ by performing a ‘dummy’ write
operation (Figure 19). The START condition is followed by the slave address (with the R/W
bit set to ‘0’) and the desired byte address. Instead of following-up with data, the master
then issues a second START, followed by the ‘Current Address Read’ sequence, as
described in Section 7.10.3.1.
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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