SE97 Datasheet, PDF (42/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 30. SMBus AC characteristics
V_DD = 1.7 V to 3.6 V; T_amb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design.
The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I²C-bus from DC
to 400 kHz.
Symbol Parameter
Conditions
Standard mode
Fast mode
Unit
Min
Max
Min
Max
f_SCL
t_HIGH
t_LOW
t_to(SMBus)
SCL clock frequency
HIGH period of the SCL clock 70 % to 70 %
LOW period of the SCL clock 30 % to 30 %
SMBus time-out time
LOW period to reset
SMBus
10^[1]
100
10^[1]
400 kHz
4000
-
600
- ns
4700
-
1300
- ns
25
35
25
35 ms
t_r
rise time of both SDA and
SCL signals
-
1000
20
300 ns
t_f
fall time of both SDA and SCL
signals
-
300
-
300 ns
t_SU;DAT
t_h(i)(D)
t_HD;DAT
t_SU;STA
data set-up time
data input hold time
data hold time
set-up time for a repeated
START condition
250
-
100
[2][3]
0
-
0
[4]
200
3450
200
[5]
4700
-
600
- ns
- ns
900 ns
- ns
t_HD;STA
hold time (repeated) START 30 % of SDA to
condition
70 % of SCL
[6]
4000
-
600
- ns
t_SU;STO
set-up time for STOP
condition
4000
-
600
- ns
t_BUF
bus free time between a
STOP and START condition
[2]
4700
-
1300
- ns
t_SP
pulse width of spikes that
must be suppressed by the
input filter
-
50
-
50 ns
t_VD;DAT data valid time
t_f(o)
output fall time
t_POR
power-on reset pulse time
EEPROM power-up timing^[7]
from clock
power supply falling
200
-
200
- ns
-
-
-
250 ns
0.5
-
0.5
- µs
t_pu(R)
read power-up time
t_pu(W)
write power-up time
Write cycle limits
[8]
-
1
-
1 ms
[8]
-
1
-
1 ms
T_cy(W)
write cycle time
[9]
-
10
-
10 ms
[1] Minimum clock frequency is 0 kHz if SMBus Time-out is disabled.
[2] Delay from SDA STOP to SDA START.
[3] A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the V_IH(min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
[4] Delay from SCL HIGH-to-LOW transition to SDA edges.
[5] Delay from SCL LOW-to-HIGH transition to restart SDA.
[6] Delay from SDA START to first SCL HIGH-to-LOW transition.
[7] These parameters tested initially and after a design or process change that affects the parameter.
[8] t_pu(R) and t_pu(W) are the delays required from the time V_DD is stable until the specified operation can be initiated.
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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