SE97 Datasheet, PDF (33/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.9 SMBus register
Table 25. SMBus Time-out register bit allocation
Bit
15
14
13
12
11
10
Symbol
RFU
Default
0
0
0
0
0
0
Access
R
R
R
R
R
R
Bit
7
6
5
4
3
2
Symbol STMOUT
RFU
Default
0
0
0
0
0
0
Access
R/W
R
R
R
R
R
9
8
0
0
R
R
1
0
SALRT
0
0
R
R/W
Table 26. SMBus Time-out register bit description
Bit
Symbol Description
15:8
RFU
reserved; always ‘0’
7
STMOUT SMBus time-out.
0 — SMBus time-out is enabled (default)
1 — disable SMBus time-out
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
6:1
RFU
reserved; always ‘0’
0
SALRT
SMBus Alert Response Address (ARA).
0 — SMBus ARA is enabled (default)
1 — disable SMBus ARA
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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