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SE97 Datasheet, PDF (38/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 29. DC characteristics
VDD = 1.7 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
IDD(AV)
Isd(VDD)
average supply current
supply voltage shutdown mode
current
SMBus inactive
SMBus inactive
-
250 400
µA
-
0.1 5.0
µA
VIH
VIL
VOL1
VOL2
VI(ov)
VPOR
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage 1
LOW-level output voltage 2
overvoltage input voltage
power-on reset voltage
SCL, SDA;
VDD = 3.0 V to 3.6 V
SCL, SDA;
VDD = 3.0 V to 3.6 V
VDD = 3.0 V; IOL = 3 mA
VDD = 1.7 V; IOL = 1.5 mA
pin A0; VI(ov) − VDD > 4.8 V
power supply rising
power supply falling
0.7 × VDD -
-
-
-
-
-
-
[1] 7.8
-
-
-
VDD + 1 V
0.3 × VDD V
0.4
V
0.5
V
10
V
1.7
V
SE97PW, SE97TK
0.1
-
-
V
SE97TL, SE97TP
0.6
-
-
V
IOL(sink)EVENT LOW-level output sink current on
pin EVENT
VOL1 = 0.4 V
SE97PW, SE97TK
2
-
-
mA
SE97TL, SE97TP
6
-
-
mA
IOL(sink)(SDA) LOW-level output sink current on
pin SDA
VOL2 = 0.5 V
3
-
-
mA
ILOH
HIGH-level output leakage current EVENT; VOH = VDD
−1.0
-
+1.0
µA
ILIH
HIGH-level input leakage current SDA, SCL; VI = VDD
−1.0
-
+1.0
µA
ILIL
LOW-level input leakage current
SDA, SCL; VI = VSS
−1.0
-
+1.0
µA
A0, A1, A2; VI = VSS
−1.0
-
+1.0
µA
Ci(SCL/SDA) SCL and SDA input capacitance
-
5
10
pF
IL
leakage current
on A0, A1, A2
-
1
-
µA
Ipd
pull-down current
internal; A0, A1, A2 pins;
-
VI = 0.3VDD to VDD
-
4.0
µA
ZIL
LOW-level input impedance
pins A0, A1, A2; VI < 0.3VDD
30
-
-
kΩ
ZIH
HIGH-level input impedance
pins A0, A1, A2
800
-
-
kΩ
[1] High-voltage input voltage applied to pin A0 during RWP and CRWP operations. The JEDEC specification is 7 V (min.) and 10 V (max.),
but since the SE97 EEPROM write works only down to 3.0 V, the condition of VI(ov) > 4.8 V + VDD or > 4.8 V + 3.0 V was applied and the
minimum voltage changed to 7.8 V. If VDD is 3.6 V then the minimum voltage is 8.4 V.
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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