SE97 Datasheet, PDF (34/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
9. Application design-in information
In a typical application, the SE97 behaves as a slave device and interfaces to a bus
master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host,
and asserts when the temperature reading exceeds the programmed values in the alarm
registers. The A0, A1 and A2 pins are directly connected to V_DD or V_SS without any pull-up
resistors. The SDA and SCL serial interface pins are open-drain I/Os that require pull-up
resistors, and are able to sink a maximum of 3 mA with a voltage drop less than 0.4 V.
Typical pull-up values for SCL and SDA are 10 kΩ, but the resistor values can be changed
in order to meet the rise time requirement if the capacitance load is too large due to
routing, connectors, or multiple components sharing the same bus.
slave
V_DD
SE97
A0
A1
A2
V_SS
3.3 V
10 kΩ
(3×)
SCL
SDA
EVENT
master
HOST
CONTROLLER
002aab354
Fig 22. Typical application showing SE97 interfacing with 3.3 V host
0.1 µF
V_DD
SE97
A0
A1
A2 _VSS
3.3 V
10 kΩ
SCL
SDA
EVENT
10 kΩ
mother board
0.1 µF
V_CC(B) V_CC(A) ^{10 kΩ}
B2
A2
PCA9509
B1
A1
10 kΩ
1.1 V
0.1 µF
SCL
SDA
EVENT
HOST
CONTROLLER
EN
Fig 23. SE97 interfacing with 1.1 V host controller
002aad262
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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