SE97 Datasheet, PDF (23/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8.2 Capability register (00h, 16-bit read-only)
Table 9. Capability register (address 00h) bit allocation
Bit
15
14
13
12
11
Symbol
RFU
Default
0
0
0
0
0
Access
R
R
R
R
R
Bit
7
6
5
4
3
Symbol
RFU
VHV
TRES
Default
0
0
0^[1]
1
0
Access
R
R
R
R
R
10
0
R
2
WRNG
1
R
9
0
R
1
HACC
1
R
8
0
R
0
BCAP
1
R
[1] The SE97 A0 pin can support up to 10 V, but the final die was already taped out before the JC42.4 ballot 1435.00 register change could
be implemented. Bit 5 is changed from ‘0’ to ‘1’ on the future 1.7 V to 3.6 V SE97B.
Table 10. Capability register (address 00h) bit description
Bit
Symbol
Description
15:6
RFU
Reserved for future use; must be zero.
5
VHV
High voltage standoff for pin A0.
0 — default
1 — This part can support a voltage up to 10 V on the A0 pin to
support JC42.4 ballot 1435.00.
4:3
TRES
Temperature resolution.
10 — 0.125 °C LSB (11-bit)
2
WRNG
Wider range.
1 — can read temperatures below 0 °C and set sign bit accordingly
1
HACC
Higher accuracy (set during manufacture).
1 — B grade accuracy
0
BCAP
Basic capability.
1 — has Alarm and Critical Trips interrupt capability
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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