SE97 Datasheet, PDF (19/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
slave address (memory)
dummy byte address
dummy data
SDA S 0 1 1 0 A2 A1 A0 1 A X X X X X X X X A X X X X X X X X A P
START condition
R/W acknowledge⁽¹⁾
from slave
no acknowledge⁽¹⁾
from slave
X = Don’t Care
(1) Refer to Table 7 regarding the exact state of the acknowledge bit.
Fig 17. Software Write Protect (read)
no acknowledge⁽¹⁾
from slave
STOP condition
002aac644
7.10.2.1 Permanent Write Protection (PWP)
If the software write-protection has been set with the PWP instruction, the first 128 bytes
of the memory are permanently write-protected. This write-protection cannot be cleared
by any instruction, or by power-cycling the device. Also, once the PWP instruction has
been successfully executed, the device no longer acknowledges any instruction (with 4-bit
fixed address of 0110b) to access the write-protection settings.
7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP)
If the software write-protection has been set with the RWP instruction, it can be cleared
again with a CRWP instruction.
The two instructions, RWP and CRWP have the same format as a Byte Write instruction,
but with a different setting for the hardware address pins (as shown in Table 5). Like the
Byte Write instruction, it is followed by an address byte and a data byte, but in this case
the contents are all ‘Don’t Care’ (Figure 16). Another difference is that the voltage, V_I(ov),
must be applied on the A0 pin, and specific logical levels must be applied on the other two
(A1 and A2), as shown in Table 5.
Table 6. Acknowledge when writing data or defining write protection
Instructions with R/W bit = 0.
Status
Instruction
ACK Address
ACK
Permanently
protected
Protected with
RWP
Not protected
PWP, RWP or CRWP
page or byte write in
lower 128 bytes
RWP
CRWP
PWP
page or byte write in
lower 128 bytes
PWP or RWP
CRWP
page or byte write
NACK
ACK
NACK
ACK
ACK
ACK
ACK
ACK
ACK
not significant
address
not significant
not significant
not significant
address
not significant
not significant
address
NACK
ACK
NACK
ACK
ACK
ACK
ACK
ACK
ACK
Data byte
not significant
data
not significant
not significant
not significant
data
not significant
not significant
data
ACK
NACK
NACK
NACK
ACK
ACK
NACK
ACK
ACK
ACK
Write cycle
(T_cy(W))
no
no
no
yes
yes
no
yes
no
yes
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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