SE97 Datasheet, PDF (16/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
7.10 EEPROM operation
The 2-kbit EEPROM is organized as either 256 bytes of 8 bits each (byte mode), or
16 pages of 16 bytes each (page mode). Accessing the EEPROM in byte mode or page
mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported.
Communication with the EEPROM is via the 2-wire serial I²C-bus or SMBus. Figure 13
provides an overview of the EEPROM partitioning.
00h 01h
…
07h
FFh
no write protect
80h
7Fh
16 pages or
256 bytes
write protect
by software
0Fh
00h
Fig 13. EEPROM partitioning
8 pages or
128 bytes
1 page
or 16 bytes
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The EEPROM can be read over voltage range 1.7 V to 3.6 V, but all write operations must
be done 3.0 V to 3.6 V.
7.10.1 Write operations
7.10.1.1 Byte Write
In Byte Write mode the master creates a START condition and then broadcasts the slave
address, byte address, and data to be written. The slave acknowledges all 3 bytes by
pulling down the SDA line during the ninth clock cycle following each byte. The master
creates a STOP condition after the last ACK from the slave, which then starts the internal
write operation (see Figure 14). During internal write, the slave will ignore any read/write
request from the master.
slave address (memory)
word address
SDA S 1 0 1 0 A2 A1 A0 0 A
A
START condition
R/W acknowledge
from slave
acknowledge
from slave
Fig 14. Byte Write timing
data
DATA
AP
acknowledge
from slave
STOP condition;
write to the memory is performed
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SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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