SE97 Datasheet, PDF (27/54 Pages) NXP Semiconductors – DDR memory module temp sensor with integrated SPD, 3.3 V

NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
Table 12. Configuration register (address 01h) bit description …continued
Bit Symbol Description
0
EMD
EVENT Mode.
0 — comparator output mode (default)
1 — interrupt mode
When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot
be altered until unlocked.
Table 13. Hysteresis enable
Action Below Alarm Window bit (bit 13)
Temperature Threshold
slope
temperature
sets
falling
clears rising
T_trip(l) − T_hys
T_trip(l)
Above Alarm Window bit (bit 14)
Temperature Threshold
slope
temperature
rising
falling
T_trip(u)
T_trip(u) − T_hys
Above Critical Trip bit (bit 15)
Temperature Threshold
slope
temperature
rising
falling
T_th(crit)
T_th(crit) − T_hys
temperature
critical alarm
threshold
upper alarm
threshold
current temperature
hysteresis
hysteresis
lower alarm
threshold
hysteresis
Above Critical Trip
(register 05h;
bit 15 = ACT bit)
Above Alarm Window
(register 05h;
bit 14 = AAW bit)
Below Alarm Window
(register 05h;
set
bit 13 = BAW bit)
clear
clear
Fig 21. Hysteresis: how it works
set
set
clear
time
clear
clear
002aac799
SE97_5
Product data sheet
Rev. 05 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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