MC68HC705P9 Datasheet, PDF (84/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports _{Port D}
When bit DDRDx is a logic one, reading address $0003 reads the PDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 1 summarizes the
operation of the port D pins.
Table 4. Port D Pin Operation
Data Direction Bit
0
I/O Pin Mode
Input, Hi-Z⁽¹⁾
Accesses to Data Bit
Read
Pin
Write
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Parallel I/O Ports
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