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MC68HC705P9 Datasheet, PDF (114/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit　
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Timing
114
SIOP Timing
SCK
tSCK
tSCKL
tV
tHO
SDO
MSB
SDI
MSB
BIT 1
tH
tS
VALID
DATA
LSB
LSB
Figure 5. SIOP Timing
Table 1. SIOP Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol Min Max
Frequency of Operation
Master
Slave
fSIOP(M)
fSIOP(S)
fOSC/64 fOSC/8
dc
525
Cycle Time
Master
Slave
tSCK(M)
tSCK(S)
4.0
4.0
— 1920
Clock (SCK) Low Time (fOP = 2.1 MHz)(3)(4)
tSCKL
932
—
SDO Data Valid Time
tV
—
200
SDO Hold Time
tHO
0
—
SDI Setup Time
tS
100
—
SDI Hold Time
tH
100
—
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted.
2. tCYC = 1 ÷ fOP
3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 2.1 MHz maximum
4. In master mode, the frequency of SCK is fOP ÷ 4.
Unit
MHz
kHz
tCYC(2)
ns
ns
ns
ns
ns
ns
SIOP
8-siop_a
MOTOROLA
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