MC68HC705P9 Datasheet, PDF (80/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports _{Port C}
The port C data register reads normally while the ADC is on, except
that the bit corresponding to the currently selected ADC input pin
reads as logic zero.
Writing to bits PC7–PC3 while the ADC is on can produce
unpredictable ADC results.
Data Direction
Data direction register C determines whether each port C pin is an input
Register C (DDRC) or an output.
$0006 Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 9. Data Direction Register C (DDRC)
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Writing to bits DDRC7–DDRC3 while the ADC is on can produce
unpredictable ADC results.
Figure 10 shows the I/O logic of port C.
10-mc68hc705p9
80
Parallel I/O Ports
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