MC68HC705P9 Datasheet, PDF (78/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports _{Port B}
READ DATA DIRECTION REGISTER B ($0005)
WRITE DATA DIRECTION REGISTER B ($0005)
RESET
DDRBx
WRITE PORT B DATA REGISTER ($0001)
PBx
PBx
READ PORT B DATA REGISTER ($0001)
Figure 7. Port B I/O Logic
Writing a logic one to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic zero disables the output buffer.
When bit DDRBx is a logic one, reading address $0001 reads the PBx
data latch. When bit DDRBx is a logic zero, reading address $0001
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 1 summarizes the
operation of the port B pins.
Table 2. Port B Pin Operation
Data Direction Bit
0
I/O Pin Mode
Input, Hi-Z⁽¹⁾
Accesses to Data Bit
Read
Pin
Write
Latch⁽²⁾
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Parallel I/O Ports
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