MC68HC705P9 Datasheet, PDF (62/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Resets and Interrupts _Interrupts
Timer Overflow
Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF is in the timer status register, and TOIE is in the timer control
register.
Interrupt
Processing
The CPU takes the following actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 6
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $1FFC and $1FFD (software interrupt vector)
– $1FFA and $1FFB (external interrupt vector)
– $1FF8 and $1FF9 (timer interrupt vector)
The return from interrupt (RTI) instruction causes the CPU to recover the
CPU registers from the stack as shown in Figure 6.
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Resets and Interrupts
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