MC68HC705P9 Datasheet, PDF (74/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports _{Port A}
Data Direction
Data direction register A determines whether each port A pin is an input
Register A (DDRA) or an output.
$0004 Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all eight port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4 shows the I/O logic of port A.
READ DATA DIRECTION REGISTER A ($0004)
WRITE DATA DIRECTION REGISTER A ($0004)
RESET
DDRAx
WRITE PORT A DATA REGISTER ($0000)
PAx
PAx
READ PORT A DATA REGISTER ($0000)
Figure 4. Port A I/O Circuit
4-mc68hc705p9
74
Parallel I/O Ports
MOTOROLA