MC68HC705P9 Datasheet, PDF (60/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Resets and Interrupts _Interrupts
IRQ/V_PP
LEVEL-SENSITIVE TRIGGER
(MOR OPTION)
V_DD
D
Q
CK
CLR
(FROM CCR)
I
Figure 4. External Interrupt Logic
EXTERNAL
INTERRUPT
REQUEST
RESET
VECTOR FETCH
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ/V_PP pin is a programmable
option. The IRQ/V_PP pin can be negative-edge triggered or
negative-edge- and low-level triggered. The level-sensitive triggering
option allows multiple external interrupt sources to be wire-ORed to the
IRQ/V_PP pin. An external interrupt request, shown in Figure 5, is latched
as long as any source is holding the IRQ/V_PP pin low.
IRQ/V_PP PIN
IR.Q₁
.
.
IRQ_n
IRQ (INTERNAL)
t_ILIL
t_ILIH
t_ILIH
Figure 5. External Interrupt Timing
6-mc68hc705p9
60
Resets and Interrupts
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