MC68HC705P9 Datasheet, PDF (83/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports
Port D
Data Direction
Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output.
$0007 Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
DDRD5
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12. Data Direction Register D (DDRD)
DDRD5 — Data Direction Register D Bit
This read/write bit controls the data direction of pin PD5. Reset clears
DDRD5, configuring PD5 as an input.
1 = PD5 configured as output
0 = PD5 configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13 shows the I/O logic of port D.
READ DATA DIRECTION REGISTER D ($0007)
WRITE DATA DIRECTION REGISTER D ($0007)
RESET
DDRDx
WRITE PORT D DATA REGISTER ($0003)
PDx
PDx
READ PORT D DATA REGISTER ($0003)
Figure 13. Port D I/O Logic
Writing a logic one to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic zero disables the output buffer.
13-mc68hc705p9
MOTOROLA
Parallel I/O Ports
83