MC68HC705P9 Datasheet, PDF (117/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

SIOP
I/O Registers
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
1 = SIOP enabled
0 = SIOP disabled
MSTR — Master Mode Select
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR
can be set at any time regardless of the state of SPE. Reset clears
MSTR.
1 = Master mode selected
0 = Slave mode selected
11-siop_a
MOTOROLA
SIOP
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