MC68HC705P9 Datasheet, PDF (112/156 Pages) Motorola, Inc – HCMOS Microcontroller Unit

PB5/SDO
SIOP _Operation
Figure 3 shows the timing relationships among the serial clock, data
input, and data output. The state of the serial clock between
transmissions is a logic one. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
SERIAL CLOCK
SAMPLE INPUT
DATA OUTPUT
(MSB-FIRST OPTION)
DATA OUTPUT
(LSB-FIRST OPTION)
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB
Figure 3. SIOP Data/Clock Timing
The first falling edge on PB7/SCK begins a transmission. At this time the
first bit of received data is accepted at the PB6/SDI pin and the first bit
of transmitted data is presented at the PB5/SDO pin.
The PB5/SDO pin is the SIOP data output. Between transfers, the state
of the PB5/SDO pin reflects the value of the last bit shifted out on the
previous transmission, if there was one. To preset the beginning state,
write to the corresponding port data bit before enabling the SIOP. On the
first falling edge on the PB7/SCK pin, the first data bit to be shifted out
appears at the PB5/SDO pin.
After SPE is set, the PB5/SDO output driver can be disabled by writing
a zero to the corresponding data direction register bit of the port, thereby
configuring PB5/SDO as a high-impedance input.
6-siop_a
112
SIOP
MOTOROLA