MRF24J40_08 Datasheet, PDF (98/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.8.1.4
Configuring Beacon-Enabled PAN
Coordinator
The following steps configure the MRF24J40 as a
coordinator in a beacon-enabled network:
1. Set the PANCOORD (RXMCR 0x00<3>) bit = 1
to configure as PAN coordinator.
2. Set the SLOTTED (TXMCR 0x11<5>) bit = 1 to
use Slotted CSMA-CA mode.
3. Load the beacon frame into the TXBFIFO
(0x080-0x0FF).
4. Set the TXBMSK (TXBCON1 0x25<7>) bit = 1 to
mask the beacon interrupt mask.
5. Program the CAP end slot (ESLOTG1
0x13<3:0>) value. If the coordinator supports
Guaranteed Time Slot operation, refer to
Section 3.8.1.5 “Configuring Beacon-Enabled
GTS Settings for PAN Coordinator” below.
6. Calibrate the Sleep Clock (SLPCLK) frequency.
Refer to Section 3.15.1.2 “Sleep Clock
Calibration”.
7. Set WAKECNT (SLPACK 0x35<6:0>)
value = 0x5F to set the main oscillator (20 MHz)
start-up timer value.
8. Program the Beacon Interval into the Main Coun-
ter, MAINCNT (0x229<1:0>, 0x228, 0x227,
0x226), and Remain Counter, REMCNT (0x225,
0x224), according to BO and SO values. Refer to
Section 3.15.1.3 “Sleep Mode Counters”.
9. Configure the BO (ORDER 0x10<7:4>) and SO
(ORDER 0x10<3:0>) values. After configuring
BO and SO, the beacon frame will be sent
immediately.
3.8.1.5
Configuring Beacon-Enabled GTS
Settings for PAN Coordinator
The following steps configure the MRF24J40 as a
coordinator in a beacon-enabled network with
Guaranteed Time Slots:
1. Set the GTSON (GATECLK 0x26 <3>) bit = 1 to
enable the GTS FIFO clock.
2. Based on the number of GTSs that are active for
the current superframe, program the end slot
value of each GTS into the ESLOT registers as
shown in Table 3-9.
TABLE 3-9: PROGRAMMING END SLOT
VALUES
GTS Number
Register
CAP
GTS1
GTS2
GTS3
GTS4
GTS5
GTS6
GTS7
ESLOTG1 0x13<3:0>
ESLOTG1 0x13<7:4>
ESLOTG23 0x1E<3:0>
ESLOTG23 0x1E<7:4>
ESLOTG45 0x1F<3:0>
ESLOTG45 0x1F<7:4>
ESLOTG67 0x20<3:0>
If 7^th GTS exists, the end slot must
be 15
3. Set the GTSSWITCH (TXPEND 0x21<1>) bit = 1
so that if a TXGTS1FIFO or TXGTS2FIFO trans-
mission error occurs, it will switch to another
TXGTSxFIFO.
DS39776B-page 96
Preliminary
© 2008 Microchip Technology Inc.