MRF24J40_08 Datasheet, PDF (68/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-72: SLPCON0: SLEEP CLOCK CONTROL 0 REGISTER (ADDRESS: 0x211)
R/W-0
r
bit 7
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
INTEDGE⁽¹⁾
R/W-0
SLPCLKEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
bit 1
bit 0
Reserved: Maintain as ‘0’
INTEDGE: Interrupt Edge Polarity bit⁽¹⁾
1 = Rising edge
0 = Falling edge (default)
SLPCLKEN: Sleep Clock Enable bit
1 = Disabled
0 = Enabled (default)
Note 1: Ensure that the interrupt polarity matches the interrupt pin polarity on the host microcontroller.
REGISTER 2-73: SLPCON1: SLEEP CLOCK CONTROL 1 REGISTER (ADDRESS: 0x220)
R/W-0
r
bit 7
R/W-0
r
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4-0
Reserved: Maintain as ‘0’
CLKOUTEN: CLKOUT Pin Enable bit
The CLKOUT pin 26 feature has been discontinued. It is recommended that it be disabled.
1 = Disable (recommended)
0 = Enable (default)
SLPCLKDIV<4:0>: Sleep Clock Divisor bits
Sleep clock is divided by 2ⁿ, where n = SLPCLKDIV.⁽¹⁾ Default value: 0x00.
Note 1: If the Sleep Clock Selection, SLPCLKSEL (0x207<7:6), is the internal oscillator (100 kHz), set
SLPCLKDIV to a minimum value of 0x01.
DS39776B-page 66
Preliminary
© 2008 Microchip Technology Inc.