MRF24J40_08 Datasheet, PDF (145/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
INDEX
A
Absolute Maximum Ratings ............................................. 135
AC Characteristics
Receiver ................................................................... 136
Transmitter ............................................................... 137
Acknowledgement ............................................................ 112
Associated Registers ............................................... 113
Antenna/Balun ................................................................. 129
Applications ...................................................................... 129
External PA/LNA Control ......................................... 130
B
Battery Monitor ................................................................. 114
Beacon-Enabled Network .................................................. 93
Bill of Materials ................................................................. 134
Block Diagrams
20 MHz Main Oscillator Crystal Circuit ........................ 8
32 kHz External Oscillator Crystal Circuit .................... 9
Beacon-Enabled Coordinator Sleep Time Line ........ 118
Beacon-Enabled Device Sleep Time Line ............... 119
Example Circuit ........................................................ 129
External PA/LNA ...................................................... 130
IEEE 802.15.4 PHY Packet and MAC
Frame Structure ................................................... 4
Interrupt Logic ............................................................ 87
MRF24J40 Architecture ............................................... 6
Nonbeacon-Enabled (Coordinator or Device)
Sleep Time Line ............................................... 120
Sleep Clock Generation ........................................... 115
Sleep Mode Counters .............................................. 117
Superframe Structure ................................................. 94
Wireless Node .............................................................. 3
C
CCA
Associated Registers ................................................. 89
Mode 1 ....................................................................... 89
Mode 2 ....................................................................... 89
Mode 3 ....................................................................... 89
Channel Selection .............................................................. 88
Associated Registers ................................................. 88
Clear Channel Assessment (CCA) .................................... 89
Control Register Description .............................................. 14
Control Registers
Mapping, Long Address ............................................. 14
Mapping, Short Address ............................................ 14
CSMA-CA .......................................................................... 99
Associated Registers ............................................... 101
Slotted Mode ............................................................ 100
Unslotted Mode .......................................................... 99
Current Consumption ....................................................... 136
Customer Change Notification Service ............................ 146
Customer Notification Service .......................................... 146
Customer Support ............................................................ 146
D
Device Overview ............................................................ 3, 85
E
Electrical Characteristics .................................................. 135
Energy Detection (ED) ....................................................... 90
Errata ................................................................................... 2
Example SPI Slave Mode Requirements ......................... 137
External PA/LNA
Associated Registers ............................................... 131
G
Generation ....................................................................... 115
GTSFIFO State Diagram ................................................... 95
H
Hardware Description .......................................................... 5
I
IEEE 802.15.4-2003 Standard ............................................. 4
Impedance
Measured ................................................................. 129
Initialization ........................................................................ 86
Associated Registers ................................................. 86
Interframe Spacing (IFS) ................................................. 102
Associated Registers ............................................... 102
Internet Address .............................................................. 146
Interrupts ........................................................................... 87
L
Link Quality Indication (LQI) .............................................. 93
Long Address Control Register Summary ......................... 16
M
MAC Timer ....................................................................... 122
Associated Registers ............................................... 122
Memory Map ...................................................................... 11
Memory Organization ........................................................ 11
Long Address Register Interface ............................... 13
Short Address Register Interface .............................. 12
Microchip Internet Web Site ............................................. 146
N
Nonbeacon-Enabled Network ............................................ 93
O
Oscillator
100 kHz Internal .......................................................... 9
20 MHz Main ............................................................... 8
23 kHz External Crystal ............................................... 8
P
Packaging ........................................................................ 139
Details ...................................................................... 140
Marking .................................................................... 139
PCB
Layout Design .......................................................... 132
Phase Lock Loop (PLL) ....................................................... 8
Pin Descriptions ................................................................... 7
CS (Serial Interface Enable) ........................................ 7
GND (Ground, Digital Circuit) ...................................... 7
GND (Ground, PLL) ..................................................... 7
GND (Guard Ring Ground) .......................................... 7
GPIO0 (External PA Enable) ....................................... 7
GPIO1 (External TX/RX Switch Control) ..................... 7
GPIO2 (External TX/RX Switch Control) ..................... 7
GPIO3 (General Purpose Digital I/O) .......................... 7
GPIO4 (General Purpose Digital I/O) .......................... 7
GPIO5 (General Purpose Digital I/O) .......................... 7
INT (Interrupt Pin) ........................................................ 7
LCAP (PLL Loop Filter External Capacitor) ................. 7
LPOSC1 (32 kHz Crystal Input) ................................... 7
LPOSC2 (32 kHz Crystal Input) ................................... 7
NC (No Connection) .................................................... 7
© 2006 Microchip Technology Inc.
Preliminary
DS39776A-page 143