MRF24J40_08 Datasheet, PDF (11/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

FIGURE 2-3:
CL22
CL11
32 kHz EXTERNAL
OSCILLATOR CRYSTAL
CIRCUIT
LPOSC2
32 kHz
External
X2
Crystal
Oscillator
LPOSC1
2.8 100 kHz Internal Oscillator
The 100 kHz internal oscillator requires no external
components and provides one of two Sleep clock
(SLPCLK) frequencies to Sleep mode counters. The
Sleep mode counters time the Beacon Interval (BI) and
inactive period for a beacon-enabled device and the
Sleep interval for a nonbeacon-enabled device. Refer
to Section 3.15 “Sleep” for more information.
The SLPCLK frequency is selectable between the
32 kHz external crystal oscillator or 100 kHz internal
oscillator. The 32 kHz external crystal oscillator
provides better frequency accuracy and stability than
the 100 kHz internal oscillator. It is recommended that
the 100 kHz internal oscillator be calibrated before use.
The calibration procedure is given in Section 3.15.1.2
“Sleep Clock Calibration”.
2.9 Reset (RESET) Pin
An external hardware Reset can be performed by
asserting the RESET pin 13 low. The MRF24J40 will be
released from Reset approximately 250 μs after the
RESET pin is released. The RESET pin has an internal
weak pull-up resistor.
2.10 Interrupt (INT) Pin
The Interrupt (INT) pin 16 provides an interrupt signal
to the host microcontroller from the MRF24J40. The
polarity is configured via the INTEDGE bit in the
SLPCON0 (0x211<1>) register. Interrupts have to be
enabled and unmasked before the INT pin is active.
Refer to Section 3.3 “Interrupts” for a functional
description of interrupts.
Note:
The INTEDGE polarity defaults to,
0 = Falling Edge. Ensure that the interrupt
polarity matches the interrupt pin polarity
on the host microcontroller.
MRF24J40
2.11 Wake (WAKE) Pin
The Wake (WAKE) pin 15 provides an external
wake-up signal to the MRF24J40 from the host micro-
controller. It is used in conjunction with the Sleep
modes of the MRF24J40. The WAKE pin is disabled by
default. Refer to Section 3.15.2 “Immediate Sleep
and Wake-up Mode” for a functional description of the
Immediate Sleep and Wake-up modes.
2.12 General Purpose Input/Output
(GPIO) Pins
Six GPIO pins can be configured individually for control
or monitoring purposes. Input or output selection is
configured by the TRISGPIO (0x34) register. GPIO
data can be read/written to via the GPIO (0x33)
register.
The GPIO pins have limited output drive capability.
Table 2-5 lists the individual GPIO pin source current
limits.
TABLE 2-5:
Pin
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO SOURCE CURRENT
LIMITS
Maximum Current Sourced
4 mA
1 mA
1 mA
1 mA
1 mA
1 mA
GPIO0, GPIO1 and GPIO2 can be configured to control
external PA, LNA, and RF switches by the internal RF
state machine. This allows the external PA and LNA to
be controlled by the MRF24J40 without any host micro-
controller intervention. Refer to Section 4.2 “External
PA/LNA Control” for control register configuration,
timing diagrams and application information.
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 9