MRF24J40_08 Datasheet, PDF (110/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.12.1 TX FIFOs FRAME STRUCTURE
The TX FIFOs are divided into four fields:
Header length – Used primarily in Security mode and
contains the length, in octets (bytes), of the MAC
Header (MHR). In Unsecure mode, this field is ignored.
Note:
The header length field as implemented in
the MRF24J40 is 5-bits long. Therefore,
the header length maximum value is
31 octets (bytes).
Frame length – Contains the length, in octets (bytes),
of the MAC Header (MHR) and data payload.
Header – Contains the MAC Header (MHR).
Payload – Contains the data payload.
When the individual TX FIFO is triggered, the
MRF24J40 will handle transmitting the packet using the
CSMA-CA algorithm, Acknowledgment of the packet
(optional), retransmit if Acknowledgment not received
within required time period and interframe spacing. The
MRF24J40 will add the Synchronization Header
(SHR), PHY Header (PHR) and Frame Check
Sequence (FCS) automatically. If a packet is to be
transmitted using in-line security, the Message Integrity
Code (MIC) will be appended in the data payload by the
MRF24J40. Refer to Section 3.17 “Security” for more
information about transmitting and receiving data in
Security mode. In Beacon-Enabled mode, the
MRF24J40 will handle superframe timing, transmission
of the beacon and data packets during CAP and CFP.
3.12.2 TX NORMAL FIFO
In Beacon-Enabled mode, the TX Normal FIFO is used
for the transmission of data and MAC command frames
during the Contention Access Phase (CAP) of the
superframe.
In Nonbeacon-Enabled mode, the TX Normal FIFO is
used for all transmissions.
To transmit a packet in the TX Normal FIFO, perform
the following steps:
1. The host processor loads the TX Normal FIFO
with IEEE 802.15.4 compliant data or MAC
command frame using the format shown in
Figure 3-12.
FIGURE 3-12:
FIGURE 3-12: TX NORMAL FIFO FORMAT
octets
Packet Structure
1
1
Header Frame
Length Length
(m) (m + n)
m
Header
n
Payload
TX Normal FIFO
Memory Address
0x000 0x001 0x002 – (0x002 + m – 1)
(0x002 + m) – (0x002 + m + n – 1)
2. If the packet requires an Acknowledgment, the
Acknowledgment request bit in the frame control
field should be set to ‘1’ in the MAC Header
(MHR) when the host microcontroller loads the TX
Normal FIFO, and set the TXNACKREQ
(TXNCON 0x1B<2>) bit = 1. Refer to
Section 3.13 “Acknowledgement” for more
information about Acknowledgment configuration.
3. If the frame is to be encrypted, the security
enabled bit in the frame control field should be
set to ‘1’ in the MAC Header (MHR) when the
host microcontroller loads the TX Normal FIFO,
and set the TXNSECEN (TXNCON 0x1B<1>)
bit = 1. Refer to Section 3.17 “Security” for
more information about Security modes.
4. Transmit the packet by setting the TXNTRIG
(TXNCON 0x1B<0>) bit = 1. The bit will be
automatically cleared by hardware.
5. A TXNIF (INTSTAT 0x31<0>) interrupt will be
issued. The TXNSTAT (TXSTAT 0x24<0>) bit
indicates the status of the transmission:
TXNSTAT = 1: Transmission was successful
TXNSTAT = 0: Transmission failed, retry count
exceeded
The number of retries of the most recent
transmission is contained in the TXNRETRY
(TXSTAT 0x24<7:6>) bits. The CCAFAIL
(TXSTAT 0x24<5>) bit = 1 indicates if the failed
transmission was due to the channel busy
(CSMA-CA timed out).
DS39776B-page 108
Preliminary
© 2008 Microchip Technology Inc.