MRF24J40_08 Datasheet, PDF (35/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-25: TXNCON: TRANSMIT NORMAL FIFO CONTROL REGISTER (ADDRESS: 0x1B)
R/W-0
r
bit 7
R/W-0
r
R/W-0
r
R-0
FPSTAT⁽¹⁾
R/W-0
R/W-0
R/W-0
INDIRECT⁽⁴⁾ TXNACKREQ^(2,4) TXNSECEN^(3,4)
W-0
TXNTRIG
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved: Maintain as ‘0’
FPSTAT: Frame Pending Status bit⁽¹⁾
Status of the frame pending bit in the received Acknowledgement frame.
1 = Frame pending bit = 1
0 = Frame pending bit = 0
INDIRECT: Activate Indirect Transmission bit (coordinator only)⁽⁴⁾
1 = Indirect transmission enabled
0 = Indirect transmission disabled (default)
TXNACKREQ: TX Normal FIFO Acknowledgement Request bit^(2,4)
Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received,
retransmit.
1 = Acknowledgement requested
0 = No Acknowledgement requested (default)
TXNSECEN: TX Normal FIFO Security Enabled bit^(3,4)
1 = Security enabled
0 = Security disabled (default)
TXNTRIG: Transmit Frame in TX Normal FIFO bit
1 = Transmit the frame in the TX Normal FIFO; bit is automatically cleared by hardware
Note 1:
2:
3:
4:
Refer to IEEE 802.15.4™-2003 Standard, Section 7.2.1.1.3 “Frame Pending Subfield”.
Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.4 “Acknowledgement Request Subfield”.
Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.2 “Security Enabled Subfield”.
Bit is cleared at the next triggering of TXN FIFO.
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 33