MRF24J40_08 Datasheet, PDF (127/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.17.2 MAC SUBLAYER RECEIVE
DECRYPTION
To receive and decrypt a secured frame from the
RXFIFO, perform the following steps:
1. When a packet is received and the security
enable bit = 1 in the frame control field, the
FIGURE 3-22:
SECURITY RX FIFO FORMAT
MRF24J40 issues a Security Interrupt, SECIF
(INTSTAT 0x31<4>). The Security Interrupt
indicates to the host microcontroller that the
received frame was secured. The host micro-
controller can choose to decrypt or ignore the
frame. The format of the received frame is
shown in Example 3-22.
RXFIFO
RXFIFO Address:
1
Frame
Length
(m+n+2)
0x300
m
Header (MHR)
0x301 to (0x301 + m – 1)
n
Data Payload (MSDU)
(0x301 + m) to (0x301 + m + n – 1)
2
1
1
octets
FCS
LQI
RSSI
(0x301 + m + n + 3)
(0x301 + m + n + 2)
(0x301 + m + n) to (0x301 + m + n + 1)
2. If the decryption should be ignored, set the
SECIGNORE (SECCON0 0x2C<7>) bit = 1.
The encrypted packet can be discarded or read
from the RXFIFO and processed in the upper
layers.
3. The host microcontroller loads the security key
into the RX FIFO Security Key memory location
as shown in Table 3-25.
TABLE 3-25:
FIFO
RX FIFO
DECRYPTION SECURITY KEY
AND CONTROL REGISTER
BITS
Security Key Memory
Address
0x2B0-0x2BF
4. Select the security suite and program the
RXCIPHER (SECCON0 0x2C<5:3>) bits. The
security suite selection values are shown in
Table 3-24.
5. Start the decryption by setting the SECSTART
(SECCON0 0x2C<6>) bit = 1.
6. When the decryption process is complete, a
Receive Interrupt (RXIF 0x31<3>) is issued.
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 125