MRF24J40_08 Datasheet, PDF (15/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
2.14.2 LONG ADDRESS REGISTER
INTERFACE
The long address memory space contains control
registers and FIFOs with a 10-bit address range of
0x000 to 0x38F. Figure 2-9 shows a long address read
and Figure 2-10 shows a long address write. The 12-bit
FIGURE 2-9:
LONG ADDRESS READ
SPI transfer begins with a ‘1’ to indicate a long address
transaction. It is followed by the 10-bit register address,
Most Significant bit (MSb) first. The 12^th bit indicates if
it is a read (‘0’) or write (‘1’) transaction.
CS
SCK
SDI
SDO
1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0
X
D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 2-10:
LONG ADDRESS WRITE
CS
SCK
SDI
SDO
1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1
X
D7 D6 D5 D4 D3 D2 D1 D0
© 2008 Microchip Technology Inc.
Preliminary
DS39776B-page 13