MRF24J40_08 Datasheet, PDF (72/152 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-80: MAINCNT2: MAIN COUNTER 2 REGISTER (ADDRESS: 0x228)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MAINCNT<23:16>: Main Counter bits
Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI)
and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices.
Units: SLPCLK.⁽¹⁾
Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and
Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
REGISTER 2-81: MAINCNT3: MAIN COUNTER 3 REGISTER (ADDRESS: 0x229)
W-0
STARTCNT
bit 7
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
r
R/W-0
MAINCNT25
R/W-0
MAINCNT24
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-2
bit 1-0
STARTCNT: Start Sleep Mode Counters bits
1 = Trigger Sleep mode for Nonbeacon Enable mode (BO = 0xF and Slotted = 0). Bit automatically clears
to ‘0’.
Reserved: Maintain as ‘0’
MAINCNT<25:24>: Main Counter bits
Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI) and
inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices. Units:
SLPCLK.⁽¹⁾
Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and
Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
DS39776B-page 70
Preliminary
© 2008 Microchip Technology Inc.